Complexities of layouts in three-dimensional VLSI circuits

Congestion-Driven Global Placement for Three Dimensional VLSI Circuits

The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, the problem of thermal dissipation is magnified due to the nature of these layered technologies. In this paper, we develop techniques to reduce both the local and global congestions of 3D circuit designs in order to alleviate thermal issues. Our approach consists of two...

Library-Free Technology Mapping for VLSI Circuits with Regular Layouts

Genetic Design of Vlsi Layouts

A genetic algorithm for the physical design of VLSI chips is presented The algorithm simultane ously optimizes the placement of the cells with the total routing During the placement the detailed routing is done while the global routes are opti mized by the genetic algorithm This is just opposed to the usual serial ap proach where the computation of the detailed routing is the last step in the l...

Three Dimensional VLSI-Scale Interconnects

As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processor performance. In addition, limitations in interconnect density and bandwidth serve to exacerbate current bottlenecks, particularly as computer architectures continue to reduce in size. To address these issues, we pro...

Three-dimensional integrated circuits

integrated circuits A. W. Topol D. C. La Tulipe, Jr. L. Shi D. J. Frank K. Bernstein S. E. Steen A. Kumar G. U. Singco A. M. Young K. W. Guarini M. Ieong Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architec...